5/29/2023 0 Comments Synopsys design compiler![]() According to Hasson, two types of iterations hamper productivity. Today’s challenges require a different approach, however. The answer to this issue in 2005 was the introduction of topographical technology and better correlation to layout. This meant returning to synthesis and starting over. ![]() The upshot is that designers are once again, as they did earlier in this decade, experiencing the “ping-pong” effect of doing synthesis runs and performing placement and routing only to find that they could not close timing. “As a result, the effect of coupling capacitance is greater, presenting more of a challenge for correlation and predictability.” ![]() At today’s advanced nodes, wires are fabricated taller and with less spacing between them,” says Hasson. “One is wire lengths and the other is coupling capacitance. Two major factors have risen to the top in terms of interconnect delays, says Gal Hasson, senior director of marketing for RTL synthesis, power and test automation at Synopsys. In this year’s edition of the company’s flagship product, interconnect delays are the focus of major improvements in the tool. Throughout its history as a leading logic-synthesis tool, the Synopsys Design Compiler has endeavored to stay ahead of the curve as new challenges loomed in IC implementation.
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